Hardware-Accelerated Formal Verification

A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques [3]. This paper presents a novel approach for accelerating the semi-formal verification by utilizing hardware/software co-execution. To maximize the gain from hardware acceleration, we propose two novel techniques such as hardwired conflict analysis for learning and speculative input pattern generation. Experimental results demonstrate that our FPGA-based prototype system achieved about 7x speedup compared against the software implementation of the semi-formal verifier. Also, to reduce the compilation time overhead, we propose a novel reconfigurable architecture in which every logic block has an embedded conflict analysis logic.